Field effect transistor with trench filled with insulating material and strips of semi-insulating material along trench sidewalls

ABSTRACT

In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 11/862,396,filed Sep. 27, 2007, which is a division of U.S. application Ser. No.10/931,887, filed Aug. 31, 2004, which is a division of U.S. applicationSer. No. 10/200,056, filed Jul. 18, 2002. The disclosures of U.S.application Ser. Nos. 10/200,056 and 11/862,396 are incorporated hereinby reference for all purposes.

BACKGROUND OF THE INVENTION

Power field effect transistors, e.g., MOSFETs (metal oxide semiconductorfield effect transistors), are well known in the semiconductor industry.One type of power MOSFET is a DMOS (double-diffused metal oxidesemiconductor) transistor. A cross-sectional view of a portion of a cellarray of one known variety of DMOS transistors is shown in FIG. 1. Asshown, an n-type epitaxial layer 102 overlies n-type substrate region100 to which the drain contact is made. Polysilicon-filled trenchesextend into the epitaxial layer 102 from the top surface. Thepolysilicon 106 a, 106 b in the trenches are insulated from theepitaxial layer by oxide layers 104 a, 104 b. Source regions 108 a, 108b in p-type body regions 110 a, 110 b are adjacent the trenches at thetop surface. A polysilicon gate 114 overlaps the source regions 108 a,b,extends over a surface portion of the body regions 110 a,b, and extendsover a surface area of a region between the two trenches commonlyreferred to as the mesa drift region. Metal layer 116 electricallyshorts source regions 108 a,b to body regions 110 a,b and polysilicon106 a,b in the trenches. The surface area of body regions 110 a,bdirectly underneath gate 114 defines the transistor channel region. Thearea between body regions 110 a and 110 b under gate 114 is commonlyreferred to as the JFET region.

Upon applying a positive voltage to the gate and the drain, andgrounding the source and the body regions, the channel region isinverted. A current thus starts to flow from the drain to the sourcethrough the drift region and the surface channel region.

A maximum forward blocking voltage, hereinafter referred to as “thebreakdown voltage”, is determined by the avalanche breakdown voltage ofa reverse-biased body-drain junction. The DMOS structure in FIG. 1 has ahigh breakdown voltage due to the polysilicon-filled trenches.Polysilicon 106 a,b cause the depletion layer formed as a result of thereverse-biased body-drain junction to be pushed deeper into the driftregion. By increasing the depletion region depth without increasing theelectric field, the breakdown voltage is increased without having toresort to reducing the doping concentration in the drift region whichwould otherwise increase the transistor on-resistance.

A drawback of the FIG. 1 structure is its high output capacitance Coss,making this structure less attractive for high frequency applicationssuch as radio frequency (RF) devices for power amplifiers in thewireless communication base stations. The output capacitance Coss of theFIG. 1 structure is primarily made up of: (i) the capacitance across theoxide between the polysilicon in the trenches and the drift region(i.e., Cox), in series with (ii) the capacitance across the depletionregion at the body-drift region junction. Cox is a fixed capacitancewhile the depletion capacitance is inversely proportional to thebody-drain bias.

The breakdown voltage of power MOSFETs is dependent not only upon thecell structure but also on the manner in which the device is terminatedat its outer edges. To achieve a high breakdown voltage for the deviceas a whole, the breakdown voltage at the outer edges must be at least ashigh as that for the cells. Thus, for any cell structure, acorresponding terminating structure is needed which exhibits a highbreakdown voltage.

In most amplifier circuits a significant amount of heat energy isproduced in the transistor. Only 50% efficiency is typical of the bestclass AB RF power amplifiers available. An important factor in designingpower devices for high frequency applications is thus the thermalperformance of the device. Because of the different device performancerequirements, the cells in power MOSFETs are densely packed resulting inconcentration of heat in active regions and poor heat transfer rates.The increase in temperature resulting from the poor heat transfer rateadversely effects the device performance.

Thus, a power MOSFET device with such improved characteristics as lowoutput capacitance, high breakdown voltage, and improved thermalperformance is desired.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, MOSFET cell structures andedge termination structures, and methods of manufacturing the same, aredescribed which among other features and advantages exhibit asubstantially reduced output capacitance, high breakdown voltage, andimproved thermal performance.

In one embodiment, a MOSFET comprises at least two insulation-filledtrench regions laterally spaced in a first semiconductor region to forma drift region therebetween, and at least one resistive element locatedalong an outer periphery of each of the two insulation-filled trenchregions. A ratio of a width of each of the insulation-filled trenchregions to a width of the drift region is adjusted so that an outputcapacitance of the MOSFET is minimized.

In another embodiment, a MOSFET comprises a first semiconductor regionhaving a first surface, a first trench region extending from the firstsurface into the first semiconductor region, and at least one floatingdiscontinuous region along a sidewall of the first trench region.

In another embodiment, a MOSFET comprises a first semiconductor regionhaving a first surface, a first trench region extending from the firstsurface into the first semiconductor region, and a first plurality ofregions along a sidewall of the first trench region.

In another embodiment, a MOSFET comprises a first semiconductor regionhaving a first surface, and first and second insulation-filled trenchregions each extending from the first surface into the firstsemiconductor region. Each of the first and second insulation-filledtrench regions has an outer layer of silicon of a conductivity typeopposite that of the first semiconductor region. The first and secondinsulation-filled trench regions are spaced apart in the firstsemiconductor region to form a drift region therebetween such that thevolume of each of the first and second trench regions is greater thanone-quarter of the volume of the drift region.

In another embodiment, a MOSFET comprises a first semiconductor regionover a substrate. The first semiconductor region has a first surface.The MOSFET further includes first and second insulation-filled trenchregions each extending from the first surface to a predetermined depthwithin the first semiconductor region. Each of the first and secondinsulation-filled trench regions has an outer layer of doped siliconmaterial which is discontinuous along a bottom surface of theinsulation-filled trench region so that the insulation material alongthe bottom surface of the insulation-filled trench region is in directcontact with the first semiconductor region. The outer layer of siliconmaterial is of a conductivity type opposite that of the firstsemiconductor region.

In another embodiment, a MOSFET comprises a first semiconductor regionhaving a first surface, a first insulation-filled trench regionextending from the first surface into the first semiconductor region,and strips of semi-insulating material along the sidewalls of the firstinsulation-filled trench region. The strips of semi-insulating materialare insulated from the first semiconductor region.

In accordance with an embodiment of the present invention, a MOSFET isformed as follows. A first epitaxial layer is formed over a substrate. Afirst doped region is formed in the first epitaxial layer. The firstdoped region has a conductivity type opposite that of the firstepitaxial layer. A second epitaxial layer is formed over the first dopedregion and the first epitaxial region. A first trench region is formedwhich extends from a surface of the second epitaxial layer through thefirst and second epitaxial layers and the first doped region such thatthe first doped region is divided into two floating discontinuousregions along sidewalls of the first trench region.

In another embodiment, a MOSFET is formed as follows. A first epitaxiallayer is formed over a substrate. First and second doped regions areformed in the first epitaxial layer. The first and second doped regionshave a conductivity type opposite that of the first epitaxial layer. Asecond epitaxial layer is formed over the first and second doped regionsand the first epitaxial region. First and second trench regions areformed wherein the first trench region extends through the first andsecond epitaxial layers and the first doped region such that the firstdoped region is divided into two floating discontinuous regions alongsidewalls of the first trench region, and the second trench regionextends through the first and second epitaxial layers and the seconddoped region such that the second doped region is divided into twofloating discontinuous regions along sidewalls of the second trenchregion.

In another embodiment, a MOSFET is formed as follows. A first trench isformed in a first semiconductor region. A first doped region is formedalong a bottom of the first trench. The first trench is extended deeperinto the first semiconductor region such that of the first doped regiontwo floating discontinuous regions remain along sidewalls of the firsttrench.

In another embodiment, a MOSFET is formed as follows. A firstsemiconductor region is formed over a substrate. The first semiconductorregion has a first surface. A first trench is formed which extends fromthe first surface to a predetermined depth within the firstsemiconductor region. A layer of doped silicon material is formed alongsidewalls of the trench. The layer of doped silicon material is of aconductivity type opposite that of the first semiconductor region.

The following detailed description and the accompanying drawings providea better understanding of the nature and advantages of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a cell array of a known n-channelDMOS transistor;

FIG. 2 shows a cross-sectional view of a cell array with floating pregions in accordance with one embodiment of the present invention;

FIGS. 3-1 a through 3-1 e are cross-sectional views showing an exemplaryset of process steps for forming the structure in FIG. 2;

FIGS. 3-2 a through 3-2 e are cross-sectional views showing anotherexemplary set of process steps for forming the structure in FIG. 2;

FIG. 4 shows a cross-sectional view of a cell array having elongatedfloating p regions in accordance with another embodiment of the presentinvention;

FIG. 5 shows a cross-sectional view of a cell array having a wideinsulation-filled trench in accordance with yet another embodiment ofthe present invention;

FIG. 6 shows a cross-sectional view of a cell array havinginsulation-filled trenches with a thin p layer along its outer perimeterin accordance with another embodiment of the present invention;

FIG. 7 shows a cross-sectional view of a cell array with wide trenches;

FIG. 8 shows a cross-sectional view of a cell array with p strips alongsidewalls of the trenches, in accordance with another embodiment of thepresent invention;

FIGS. 9 a through 9 e are cross-sectional views showing an exemplary setof process steps for forming the structure in FIG. 8;

FIGS. 10 a, 10 b, and 10 c show cross-sectional views of cell arrayshaving strips of semi-insulating material along sidewalls of trenches inaccordance with three embodiments of the present invention;

FIG. 11 shows a cross sectional view of a cell array wherein the trenchstructure shown in FIG. 8 is combined with a gate structure differentthan that shown in FIG. 8;

FIG. 12 shows a cross sectional view of a cell array wherein the trenchstructure shown in FIG. 8 is combined with yet another gate structure;

FIG. 13 shows a cross-sectional view of an edge termination structure inaccordance with one embodiment of the present invention; and

FIG. 14 shows a cross-sectional view of another edge terminationstructure in accordance with another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

MOSFET cell structures, edge termination structures, and methods ofmanufacturing the same are described in accordance with the presentinvention. Among other features and advantages, the cell and terminationstructures and methods of manufacturing the same exhibit a substantiallyreduced output capacitance, high breakdown voltage, and improved thermalperformance.

FIG. 2 shows a cross-sectional view of a power MOSFET cell array inaccordance with an embodiment of the present invention. As shown, bothgate terminal 205 and source terminal 207 are located along the top-sideof the device, and drain terminal 203 is located along the bottom-side.Drain terminal 203 is coupled to the lightly-doped epitaxial region 202through a highly doped region 200 serving as the drain contact.Oxide-filled trench regions 204 a, 204 b extend from the top-side to apredetermined depth in the epitaxial region 202. Discontinuous floatingp-type regions 206 a, 206 b are spaced along an outer sidewall of trenchregions 204 a,b. P-type body regions 208 a, 208 b extend from thetop-side into the epitaxial region adjacent trench regions 204 a,b. Asshown, body regions 208 a,b include highly-doped p+ regions 210 a,b,although these p+ regions may be eliminated if desired. Source regions212 a,b are formed in body regions 208 a,b as shown.

Polysilicon gates 216 overlap source regions 212 a,b, extend over thesurface area of body regions 208 a,b and over the surface area ofepitaxial region 202 between body regions 208 a and 208 b. Gates 216 areinsulated from the underlying regions by gate oxide 214. The surfacearea of body regions 208 a,b directly under gates 216 form the channelregions. Metal layer 218 overlies the top-side of the structure andforms the common source-body contact.

The area of the epitaxial region between trenches 204 a and 204 b ishereinafter referred to as drift region 209. When proper biasing isapplied to the gate, drain, and source terminals to turn on the device,current flows between drain terminal 203 and source terminal 207 throughdrain contact region 200, drift regions 209, the channel regions, sourcediffusion regions 212 a,b, and finally metal layer 218.

Comparing FIGS. 1 and 2, it can be seen that the polysilicon 106 a,b(FIG. 1) in the trenches are replaced with insulating material, thuseliminating the significant contributor to the output capacitance of theFIG. 1 structure, namely, Cox. By replacing the polysilicon with aninsulator such as silicon-dioxide, a greater portion of the space chargeregion appears across an insulator rather than silicon. Because thepermitivity of insulator is lower than that of silicon (in the case ofsilicon-dioxide, a factor of about three lower), and the area of thespace charge region along its boundaries is reduced (especially when theapplication voltage is low), the output capacitance is significantlyreduced (by at least a factor of three).

As described above, the polysilicon in the trenches of the prior artFIG. 1 structure helps improve the cell breakdown voltage by pushing thedepletion region deeper into the drift region. Eliminating thepolysilicon would thus result in lowering the breakdown voltage unlessother means of reducing the electric field are employed. Floating pregions 206 a,b serve to reduce the electric field. In FIG. 2, as theelectric field increases with the increasing drain voltage, floating pregions 206 a,b acquire a corresponding potential determined by theirposition in the space charge region. The floating potential of these pregions causes the electric field to spread deeper into the drift regionresulting in a more uniform field throughout the depth of the driftregion and thus in a higher breakdown voltage. Accordingly, similarbreakdown voltage characteristics to that of the FIG. 1 structure isachieved but with much reduced output capacitance.

Floating p regions 206 a,b have the adverse effect of reducing the widthof drift regions 209 through which current flows when the device is inthe on-state, and thus result in increased on-resistance. However, theadverse impact of the floating p regions on the on-resistance can bereduced by obtaining an optimum balance between the charge concentrationin the drift region and such features of the floating p regions as size,doping concentration, and the spacing Lp between them. For example, ahigher charge concentration in the drift region would require a smallerspacing Lp and vice versa. Further, because the floating p regionsreduce the electric field near the surface in the channel, the channellength can be reduced to improve the on-resistance and the generalperformance of the device as a high frequency amplifier.

In one embodiment wherein a breakdown voltage of 80-100V is desired,epitaxial region 202 has a doping concentration in the range of 5×10¹⁵to 1×10¹⁶ cm⁻³ and the floating p regions 206 a,b have a dopingconcentration of about 5-10 times that of the epitaxial region.

FIGS. 3-1 a through 3-1 e are cross-sectional views showing an exemplaryset of process steps for forming the structure in FIG. 2. In FIG. 3-1 a,a first n-epitaxial layer 302 is deposited on a heavily-doped substrate300 using conventional methods. P regions 306, 308 are formed byimplanting p-type impurities (such as Boron) through a mask 304. Thesize of the opening in mask 304 is dependent upon the desired width ofthe trenches and the desired width of the floating p regions which arein turn dictated by the device performance targets. In one embodiment,the target width of the trench is in the range of 1-5 μm, the width of pregions 306, 308 is at least 1 μm wider than the trench width, thelateral spacing between adjacent p regions 306 and 308 is no less than 1μm, and n-epitaxial layer 302 has a doping concentration of about 2×10¹⁶cm⁻³ and a thickness in the range of 2-5 μm.

In FIG. 3-1 b, similar steps to those in FIG. 3-1 a are carried out tofrom a second n-epitaxial layer 316 and p regions 310, 312. These stepscan be repeated depending on the desired number of floating p regions.Alternatively, the steps in FIG. 3-1 b may be eliminated to form only asingle floating p region along each trench sidewall.

In FIG. 3-1 c, a final epitaxial layer 320 to receive the device bodyand source regions is deposited. While the deposition technique used informing epitaxial regions 302, 316, and 320 is the same, the dopingconcentration of each epitaxial region can be varied depending on thedesired characteristics of the drift region. Similarly, p regions 306,308 may be implanted to have a different doping concentration than pregions 310, 312 if desired.

In FIG. 3-1 d, mask 330 and conventional silicon trench etchingtechniques are used to etch through the three epitaxial layers 302, 316,320 and through the center portion of the p regions 306, 308, 310, 312to form trenches 322 a, 322 b and corresponding floating p regions 306a,b, 308 a,b, 310 a,b, and 312 a,b. The width of the openings in mask330 determines the width of the oxide trenches relative to the width ofthe floating p regions.

After preparation of the trench surface, a relatively thin insulator(e.g., about 300-500 Å of thermal oxide) is grown on the trench surface.Trenches 322 a,b are then filled with a dielectric material such assilicon-dioxide using conventional conformal coating method and/orSpin-On Glass (SOG) method. Any low k dielectric to reduce the outputcapacitance may be used to fill trenches 322 a,b. Conventional processsteps used in forming self-aligned gate DMOS structures are then carriedout to form the gate structure as shown in FIG. 3 e.

An alternate method of manufacturing the structure in FIG. 2 isdescribed next using the simplified cross-sectional views in FIGS. 3-2 athrough 3-2 c. In FIG. 3-2 a: an initial n-epitaxial layer 342 isdeposited on a heavily-doped substrate 340; a trench 344 a is thenformed in n-epitaxial layer 342; and an implant step is then carried outto form a p region 346 at the bottom of trench 344 a, followed by adiffusion step to diffuse the p dopants further into epitaxial region342. In FIG. 3-2 b: trench 344 a is further etched past p region 346into epitaxial region 342 to form a deeper trench 344 b; and similarimplant and diffusion steps to those in FIG. 3-2 a are carried out toform p region 348 at the bottom of trench 344 b. In FIG. 3-2 c: trench344 b is etched past p region 348 into epitaxial layer 342 to form aneven deeper trench 344 c; and trench 344 c is then filled with asuitable insulator. Thus, an insulator-filled trench 344 c and floatingp regions 346 a,b and 348 a,b are formed. The remaining process stepswould be similar to those described in connection with FIG. 3-1 e.

Referring back to FIG. 2, the vertical charge control enabled by thefloating p regions allows the cells to be laterally spaced apart withoutimpacting the electrical characteristics of the device. With the cellsspaced further apart, the heat generated by each cell is distributedover a larger area and less heat interaction occurs between adjacentcells. A lower device temperature is thus achieved.

To achieve effective vertical charge control, spacing Lp (FIG. 2)between adjacent floating p regions 206 a and 206 b needs to becarefully engineered. In one embodiment, spacing Lp is determined inaccordance with the following proposition: the product of the dopingconcentration in the drift region and the spacing Lp be in the range of2×10¹² to 4×10¹² cm⁻². Thus, for example, for a drift region dopingconcentration of 5×10¹⁵ cm⁻³, the spacing Lp needs to be about 4 μm.Once an optimum spacing Lp is determined, the spacing Lc between acenter axis of adjacent trenches 204 a,b can be independently increasedwithout impacting the electrical characteristics of the device.

Two ways of achieving the increased Lc spacing while keeping Lp spacingthe same are shown in FIGS. 4 and 5. In FIG. 4, discontinuous floating pregions 406 a,b along with the source and body regions are extendedacross a large portion of the area between adjacent trenches to achievea larger Lc spacing. In one embodiment, a combined width Wt of onetrench (e.g., 404 b) and one of the first plurality of floating regions(e.g., 406 b) is greater than one-quarter of the spacing Lp. The FIG. 4embodiment is particularly useful in technologies where the trench widthWt is tightly limited to a maximum size. If the trench width is nottightly limited, then the width of the trenches can be increased toobtain a larger Lc spacing while keeping spacing Lp the same as shown inFIG. 5.

An advantage of the FIG. 5 structure over that in FIG. 4 is the loweroutput capacitance because of the smaller floating p regions, andbecause a larger portion of the depletion region occurs in the widerinsulation-filled trenches. Thus, the reduction in output capacitancedue to the wider size of the trenches can be promoted by designing thecell structure to have a high ratio of trench insulation volume to driftregion volume. A wider trench also results in improved thermalperformance. In one embodiment, the volume of the insulation in thetrench is at least one-quarter of the volume of the drift region. Thus,the larger the trench volume, the lower the output capacitance and thebetter the thermal performance of the device. However, little is gainedin making the trench wider than the thickness of the die (e.g., 100 μm).

Although FIGS. 2 through 5 show multiple floating p regions along thetrench sidewalls, the invention is not limited as such. Depending on thedevice performance requirements and design goals, only a single floatingp region may be formed along each sidewall of the trenches.

FIG. 6 shows a cross section view of a power MOSFET cell array inaccordance with another embodiment of the present invention. Thestructure in FIG. 6 is similar to that in FIG. 2 except that floating pregions 206 a,b (FIG. 2) are eliminated and p layers (or p liners) 606a,b are introduced along the outer perimeter of trenches 604 a and 604b. Similar to floating p regions 206 a,b, help spread the depletionregion deeper into the drift regions, thus improving the breakdownvoltage. P liners 606 a,b are biased to the same potential as bodyregions 608 a,b since they are in electrical contact with body regions608 a,b.

In FIG. 7, as in FIG. 5, the width Wt of the oxide trench is increasedto achieve improved thermal performance, while the Lp spacing ismaintained at the same optimum value. A drawback of the FIG. 7 structureis that p liners 706 a,b result in higher output capacitance since theycause the space charge region to follow the entire contour of thetrench. One approach in reducing the p liners' contribution to theoutput capacitance is to eliminate that portion of the p linersextending across the bottom of the trenches, as shown in FIG. 8. In thismanner, the output capacitance is reduced while the same breakdownvoltage is maintained since p strips 806 a,b (FIG. 8) spread thedepletion region deeper into the drift regions.

An exemplary set of process steps for forming the structure of FIG. 8 isshown in FIGS. 9 a through 9 c. In FIG. 9 a, a hard mask 906 along withconventional silicon trench etch methods are used to etch epitaxialregion 902 to form wide trenches 904 a, 904 b. Using the same mask, pliners 908 are formed by implanting p-type impurities at about a 45°angle into both sidewalls and bottom of the trenches using conventionalmethods. In FIG. 9 b, conventional silicon etch method is carried out toremove the portion of the p liners along the bottom of the trenches,leaving p strips 908 a,b along the sidewalls of the trenches. In FIG. 9c, a thermally-grown oxide layer 910 a,b is formed along the innersidewalls and bottom of each trench. The p-type dopants in p strips 908a,b are then activated using conventional methods. Conventional oxidedeposition steps (e.g., SOG method) are carried out to fill the trencheswith oxide, followed by planarization of the oxide surface. Conventionalprocess steps used in forming the gate structure in self-aligned gateDMOS structures are then carried out to form the full structure as shownin FIG. 9 c. Note that in the FIGS. 7 and 8 structures the thermallygrown oxide liners, similar to those in FIG. 9 c, are present but arenot shown for simplicity. The thermally grown oxide layers are includedto provide a cleaner interface between the trench insulator and the pstrips.

From the above, it can be seen that manufacturing of the FIG. 8structure is less complex than that of the FIG. 5 structure because ofthe extra steps required in forming the floating p regions in the FIG. 5structure.

The doping concentration in the p liners/strips in FIGS. 6-8 impacts theoutput capacitance of each of these structures. Highly-doped p regionslead to higher output capacitance since a higher reverse bias potentialis needed to fully deplete these p regions. Thus, a low dopingconcentration (e.g., of about 1×10¹⁷ cm⁻³) would be desirable for thesep regions. Note that these p regions have less effect on the outputcapacitance at high operating voltages.

FIGS. 10 a-10 c show cross sectional views of three power MOSFET cellarrays each of which includes strips of semi-insulating material (e.g.,oxygen-doped polysilicon SiPOS) along the trench sidewalls. In all threefigures, wide insulation-filled trenches 1004 a,b are used to achieveimproved thermal performance as in previous embodiments. Also, thesemi-insulating strips in these structures function similar topolysilicon 106 a,b in the prior art FIG. 1 in pushing the depletionregion deeper into the drift region, thus improving the breakdownvoltage.

In FIG. 10 a, strips 1006 a,b of semi-insulating material extend alongthe trench sidewalls and are insulated from epitaxial region 1002 andbody regions 1008 a,b by a layer of insulating material 1010 a,b. Strips1006 a,b are in electrical contact with the top metal layer 1018, andthus are biased to the same potential as the source and body regions.

In FIG. 10 b, strips 1020 a,b of semi-insulating material are integratedin the cell array in a similar manner to those in FIG. 10 a except thatstrips 1020 a,b are insulated from the top metal layer 1018 and thus arefloating. During operation, the potential in the space charge regioncouples to the semi-insulating strips through insulation layers 1010 a,bto bias the strips to a corresponding mostly uniform potential.

In FIG. 10 c, the insulation-filled trenches 1024 a,b extend all the waythrough epitaxial region 1002 and terminate in substrate 1000.Semi-insulating strips 1022 a,b extend along the sidewalls of thetrenches and electrically contact the source terminal through the topmetal layer 1018 and the drain terminal through substrate region 1000.Thus, the strips form a resistive connection between drain and sourceterminals. During operation, the strips acquire a linear voltagegradient with the highest potential (i.e., drain potential) at theirbottom to lowest potential (i.e., source potential) at their top. Strips1022 a,b are insulated from epitaxial regions 1002 by insulating layers1026 a,b. The gate structure in FIG. 10 c as well as in FIGS. 10 a and10 b is similar to the previous embodiments.

The semi-insulating strips in the structures of FIGS. 10 a-10 c serve asan additional tool by which the electrical characteristics of the devicecan be optimized. Depending on the application and the design targets,one structure may be preferred over the other. The resistivity of thestrips of semi-insulating material in each of the FIGS. 10 a, 10 b, 10 cstructures can be adjusted and potentially varied from the top to thebottom to enable shaping of the space charge region formation inresponse to the applied drain-source voltage V_(DS).

An exemplary set of process steps for forming the structure in FIG. 10 ais as follows. A hard mask is used to etch the silicon back to form widetrenches as in previous embodiments with wide trenches. A layer ofthermally grown oxide having a thickness in the range of 200-1000 Å isthen formed along the inner walls and bottom of the trench. About 4000 Åof conformal oxide is then deposited over the thermally grown oxidelayer. Oxygen-doped polysilicon (SiPOS) is then deposited in the trenchregions and etched to form strips 1008 a,b along the sidewalls. Thetrenches are then filled with insulation using conventional methods(e.g., SOG method), followed by planarization of the oxide surface.Conventional steps used in forming self-aligned gate DMOS structures arethen carried out to form the full cell structure as shown in FIG. 10 a.

The depth of the trenches in the different embodiments described abovemay vary depending on the desired device performance and the targetapplication for the device. For example, for high breakdown voltage(e.g., greater than 70V), the trenches may be extended deeper into theepitaxial region (e.g., to a depth of about 5 μm). As another example,the trenches can be extended all the way through the epitaxial region tomeet the substrate regions (as in FIG. 10 c). For lower voltageapplications, the p regions (e.g., the floating p regions in FIG. 2 andthe p strips in FIG. 8) need not extend deep into the epitaxial regionsince the device is not required to meet high breakdown voltages, andalso to minimize the contribution of the p regions to the outputcapacitance.

Although the trench structures in the different embodiments describedabove are shown in combination with the gate structure of conventionalDMOS cells, the invention is not limited as such. Two examples of othergate structures with which these trench structures may be combined areshown in FIGS. 11 and 12. These two cell structures have the benefit oflower gate to drain capacitance which in combination with the low outputcapacitance of the trench structures yields power devices particularlysuitable for high frequency applications.

The FIG. 11 structure is similar to that in FIG. 8 except that asubstantial portion of the gate extending over the surface of the driftregion is eliminated. Thus, the gate to drain capacitance is reduced byan amount corresponding to the eliminated portion of the gate. In theFIG. 12 structure, the trench structure in FIG. 8 is combined with thegate structure of a conventional UMOS cell. Thus, the advantages of theUMOS cell (e.g., low on-resistance) are obtained while the low outputcapacitance and improved thermal performance of the trench structure inaccordance with the present invention are maintained. In one embodimentwherein the FIG. 12 structure is intended for lower voltage applications(e.g., in the range 30-40V) the depth of p strips 1208 a,b is relativelyshallow (e.g., in the range of 1.5 μm to 3 μm).

Combining the gate structures in FIGS. 11 and 12 or any other gatestructure with the different trench structures described above would beobvious to one skilled in this art in view of this disclosure.

In the above embodiments, the vertical charge control enabled by theresistive elements located along the insulation-filled trenches allowsthe cells to be laterally spaced apart without impacting the electricalcharacteristics of the device. With the cells spaced further apart, theheat generated by each cell is distributed over a larger area and lessheat interaction occurs between adjacent cells. A lower devicetemperature is thus achieved.

Although the above embodiments show the drain to be located along thebottom-side of the die, the invention is not limited as such. Each ofthe above cell structures can be modified to become a quasi-verticallyconducting structure by including a highly-doped n-type buried layerextending along the interface between the epitaxial region and theunderlying highly-doped substrate region. At convenient locations, theburied layer is extended vertically to the top surface where it can becontacted to form the drain terminal of the device. In theseembodiments, the substrate region may be n-type or p-type depending onthe application of the MOSFET.

As mentioned earlier, edge termination structures with breakdownvoltages equal to or greater than that of the individual cells arerequired to achieve a high device breakdown voltage. In the case of theFIG. 8 structure, simulation results indicate that terminating at theouter edge of the device with a trench structure like trench 804 b wouldresult in higher electric fields due to the electric field transition upto the top surface at the outside of the outer trench. An edgetermination structure which yields the same or higher breakdown voltagethan the cell structure in FIG. 8 is shown in FIG. 13.

In FIG. 13, the active gate over the drift region between the outer twotrenches 1306 b and 1306 c is eliminated allowing the drift regionspacing Lt between these outer two trenches to be reduced to less thanthe drift region spacing Lc in the cell structures. The active gatehowever may be left in if obtaining the Lt spacing does not require itsremoval. The outer p strip 1308 d is not biased (i.e., is floating), andmay be eliminated if desired. A conventional field plate structure 1310is optionally included in FIG. 13. The termination structure in FIG. 13results in: (a) the depletion region terminating within the outer trench1306 c, thus reducing the electric field at the outside of trench 1306c, and (b) the field on the inside of outer trench 1306 c is reduced dueto short Lt spacing pushing the depletion region into the drift region.

In another embodiment, the gate structure is included between trenches1306 b and 1306 c, with spacing Lt equaling spacing Lc. In thisembodiment, the p strip immediately to the right of the gate structurebetween trenches 1306 b and 1306 c (i.e., the p strip corresponding tothe strip along the left side of trench 1306 c) is not connected to thesource and thus floats.

Other variations of the FIG. 13 embodiment are possible. For example,floating guard-rings may be used on the outside of trench 1306 c with orwithout field plate structure 1310. Although cell trenches 1306 a,b andtermination trench 1306 c are shown to be narrower than the celltrenches in FIG. 8, trenches 1306 a,b,c may be widened as in FIG. 8.Further, the width Wt of termination trench 1306 c may be designed to bedifferent than cell that of trenches 1306 a,b if desired.

FIG. 14 is a cross sectional view showing another termination structurein combination with the cell structure shown in FIG. 8. As shown, thetermination structure includes a termination trench 1408 lined with aninsulation layer 1410 along its sidewalls and bottom. A field plate 1406(e.g., from doped polysilicon) is provided over insulation layer 1410 intrench 1408, and extends laterally over the surface and away from theactive regions.

Although the above-described termination structures are shown incombination with the cell structure in FIG. 8, these and other knowntermination structures may be combined with any of the cell structuresdescribed above.

While the above is a complete description of the embodiments of thepresent invention, it is possible to use various alternatives,modifications and equivalents. For example, the different embodimentsdescribed above are n-channel power MOSFETs. Designing equivalentp-channel MOSFETs would be obvious to one skilled in the art in light ofthe above teachings. Further, p+ regions, similar to p+ regions 210 a,bin the FIG. 2 structure, may be added in the body regions of the otherstructures described herein to reduce the body resistance and preventpunch-through to the source. Also, the cross sectional views areintended for depiction of the various regions in the differentstructures and do not necessarily limit the layout or other structuralaspects of the cell array. Therefore, the scope of the present inventionshould be determined not with reference to the above description butshould, instead, be determined with reference to the appended claim,along with their full scope of equivalents.

1.-38. (canceled)
 39. A MOSFET comprising: a first semiconductor regionhaving a first surface; a first insulation-filled trench regionextending from the first surface into the first semiconductor region,the first insulation-filled trench region having sidewalls and a bottomsurface; strips of semi-insulating material extending along thesidewalls of the first insulation-filled trench region but not over atleast a center portion of the bottom surface of the firstinsulation-filled trench region, the strips of semi-insulating materialbeing insulated from the first semiconductor region; and an insulatingmaterial extending over at least the center portion of the bottomsurface of the first insulation-filled trench region.
 40. The MOSFET ofclaim 39 further comprising: a second insulation-filled trench regionextending from the first surface into the first semiconductor region,the second insulation-filled trench region having sidewalls and a bottomsurface, the second insulation-filled trench region having strips ofsemi-insulating material extending along its sidewalls but not over atleast a center portion of the bottom surface of the secondinsulation-filled trench region, the strips of semi-insulating materialbeing insulated from the first semiconductor region, the secondinsulation-filled trench region having an insulating material extendingover at least the center portion of the bottom surface of thesecond-insulation-filled trench region, wherein the first and secondinsulation-filled trench regions are spaced apart in the firstsemiconductor region to form a drift region therebetween, the volume ofeach of the first and second insulation-filled trench regions beinggreater than one-quarter of the volume of the drift region.
 41. TheMOSFET of claim 39 further comprising: a body region extending from thefirst surface into the first semiconductor region, the body region beingof a conductivity type opposite that of the first semiconductor region;a source region in the body region, the source region being of the sameconductivity type as the first semiconductor region; a second trenchregion extending from the first surface into the first semiconductorregion; and a gate in the second trench region extending across aportion of the body region and overlapping the source and the firstsemiconductor regions such that a channel region extendingperpendicularly to the first surface is formed in the body regionbetween the source and first semiconductor regions.
 42. The MOSFET ofclaim 39 further comprising: first and second body regions eachextending from the first surface into the first semiconductor region,the first body region being laterally spaced from the second body regionto form a JFET region therebetween, the first and second body regionsbeing of a conductivity type opposite that of the first semiconductorregion; and first and second source regions in the first and second bodyregions respectively, the first and second source regions being of thesame conductivity type as the first semiconductor region.
 43. The MOSFETof claim 42 further comprising a gate extending over but being insulatedfrom the JFET region and a portion of the first and second body regions,and overlapping the first and second source regions such that a channelregion is formed along a body surface of each of the first and secondbody regions between the corresponding source and JFET regions.
 44. TheMOSFET of claim 42 further comprising: a gate extending over but beinginsulated from each of the first and second body regions such that achannel region is formed along a surface of each of the first and secondbody regions between the corresponding source and JFET regions, the gatebeing discontinuous over a surface of the JFET region between the firstand second body regions.
 45. The MOSFET of claim 39 wherein the stripsof semi-insulating material are from oxygen-doped polysilicon material.46. The MOSFET of claim 39 further comprising a source region, whereinthe strips of semi-insulating material are electrically connected to thesource regions.
 47. The MOSFET of claim 39 wherein each of the strips ofsemi-insulating material is insulated from its surrounding regions. 48.The MOSFET of claim 39 wherein each of the strips of semi-insulatingmaterial is floating.
 49. The MOSFET of claim 39 further comprising adrain and a source, each of the strips of semi-insulating material beingelectrically coupled between the drain and the source.
 50. The MOSFET ofclaim 39 further comprising a drain and a source, each of the strips ofsemi-insulating material being electrically coupled between the drainand the source so that during an operating mode of the MOSFET each ofthe strips of semi-insulating material acquires a linear voltagegradient from one end of the strip to an opposite end of the strip. 51.The MOSFET of claim 39 wherein: the first semiconductor region is overand in contact with a second semiconductor region of same conductivitytype as the first semiconductor region, the second semiconductor regionhaving a higher doping concentration than the first semiconductorregion, and the strips of semi-insulating material extending through thefirst semiconductor region and terminating in the second semiconductorregion.
 52. The MOSFET of claim 39 wherein: the first semiconductorregion is over and in contact with a second semiconductor region of sameconductivity type as the first semiconductor region, the secondsemiconductor region having a higher doping concentration than the firstsemiconductor region, and the first insulation-filled trench extendingthrough the first semiconductor region and terminating in the secondsemiconductor region. 53-71. (canceled)
 72. The MOSFET of claim 39wherein a resistivity of at least one of the strips of semi-insulatingmaterial varies from one end of the strip to an opposite end of thestrip proximal the bottom surface of the first insulation-filled trenchregion.